1. Field of the Invention
The present invention relates to the fabrication of integrated circuits. More particularly, the invention relates to a process and apparatus for depositing dielectric layers on a substrate.
2. Background of the Invention
One of the primary steps in the fabrication of modem semiconductor devices is the formation of metal and dielectric films on a substrate by chemical reaction of gases. Such deposition processes are referred to as chemical vapor deposition or CVD. Conventional thermal CVD processes supply reactive gases to the substrate surface where heat-induced chemical reactions take place to produce a desired film. The high temperatures at which some thermal CVD processes operate can damage device structures having layers previously formed on the substrate. A preferred method of depositing metal and dielectric films at relatively low temperatures is plasma-enhanced CVD (PECVD) techniques such as described in U.S. Pat. No. 5,362,526, entitled xe2x80x9cPlasma-Enhanced CVD Process Using TEOS for Depositing Silicon Oxidexe2x80x9d, which is incorporated by reference herein. Plasma-enhanced CVD techniques promote excitation and/or disassociation of the reactant gases by the application of radio frequency (RF) energy to a reaction zone near the substrate surface, thereby creating a plasma of highly reactive species. The high reactivity of the released species reduces the energy required for a chemical reaction to take place, and thus lowers the required temperature for such PECVD processes.
Semiconductor device geometries have dramatically decreased in size since such devices were first introduced several decades ago. Since then, integrated circuits have generally followed the two year/half-size rule (often called Moore""s Law), which means that the number of devices that will fit on a chip doubles every two years. Today""s fabrication plants are routinely producing devices having 0.351 xcexcm and even 0.181 xcexcm feature sizes, and tomorrow""s plants soon will be producing devices having even smaller geometries.
In order to further reduce the size of devices on integrated circuits, it has become necessary to use conductive materials having low resistivity and insulators having low k (dielectric constant less than 4.0) to reduce the capacitive coupling between adjacent metal lines. Liner/barrier layers have been used between the conductive materials and the insulators to prevent diffusion of byproducts such as moisture onto the conductive material as described in International Publication Number WO 94/01885. For example, moisture that can be generated during formation of a low k insulator readily diffuses to the surface of the conductive metal and increases the resistivity of the conductive metal surface. A barrier/liner layer formed from conventional silicon oxide or silicon nitride materials can block the diffusion of the byproducts. However, the barrier/liner layers typically have dielectric constants that are significantly greater than 4.0, and the high dielectric constants result in a combined insulator that does not significantly reduce the dielectric constant.
FIG. 1A illustrates a PECVD process for depositing a barrier/liner layer as described in International Publication Number WO 94/01885. The PECVD process deposits a multi-component dielectric layer wherein a silicon dioxide (SiO2) liner layer 2 is first deposited on a patterned metal layer having metal lines 3 formed on a substrate 4. The liner layer 2 is deposited by a plasma enhanced reaction of silane (SiH4) and nitrous oxide (N2O) at 300xc2x0 C. A self-planarizing low k dielectric layer 5 is then deposited on the liner layer 2 by reaction of a silane compound and a peroxide compound. The self-planarizing layer 5 retains moisture that is removed by curing. The liner layer 2 is an oxidized silane film that has effective barrier properties when deposited in a manner which provides a dielectric constant of at least 4.5. The dielectric constant of the oxidized silane film can be decreased to about 4.1 by altering process conditions in a manner that decreases moisture barrier properties of the film. Conventional liner layers, such as SiN, have even higher dielectric constants, and the combination of low k dielectric layers with high k dielectric liner layers can provide little or no improvement in the overall stack dielectric constant and capacitive coupling.
As shown in FIG. 1B, WO 94/01885 further describes an optional SiO2 cap layer 6 that is deposited on the low k dielectric layer 5 by the reaction of silane and N2O. The cap layer 6 is also an oxidized silane film that has good barrier properties when deposited in a manner that provides a dielectric constant of about 4.5. Both the liner layer 2 and the cap layer 6 have a dielectric constant greater than 4.5 and the high dielectric constant layers substantially detract from the benefit of the low k dielectric layer 5.
As devices get smaller, liner layers and cap layers having high dielectric constants contribute more to the overall dielectric constant of a multi-component dielectric layer. Furthermore, known low k dielectric materials generally have low oxide content which makes the material inadequate as an etch stop layer during etching of vias and/or interconnects. Silicon nitride has been the etch stop material of choice for making interconnect lines in low k dielectric materials. However, the silicon nitride has a relatively high dielectric constant (dielectric constant of about 7) compared to the surrounding low k dielectric layers. It has also been discovered that the silicon nitride may significantly increase the capacitive coupling between interconnect lines, even when an otherwise low k dielectric material is used as the primary insulator. This may lead to crosstalk and/or resistance-capacitance (RC) delay that degrades the overall performance of the device. Thus, the silicon nitride etch stop layers are typically removed after etching of the underlying dielectric layers.
Ideally, a low k dielectric layer having both good barrier properties for use as a liner layer and sufficient oxide content for use as an etch stop could be identified and deposited in the same chambers as existing low k dielectric materials. Such barrier layers would not increase the overall dielectric constant of the dielectric layers, and such an etch stop layer would not have to be removed after etching the underlying layers.
U.S. Pat. No. 5,554,570 describes barrier layers for use with thermal CVD silicon oxides wherein an organosilane having a Cxe2x80x94H group is oxidized instead of silane to increase the density of deposited films and to improve adhesion between the layers. For example, a thermal CVD layer produced from tetraethoxysilane (TEOS) and ozone, may be deposited between PECVD silicon oxide films produced from an organosilicon and N2O or O2.
The barrier layers described in the ""570 patent are preferably dense silicon oxide layers having low carbon contents. The dense layers are deposited using 400 W of high frequency RF power although the use of low frequency RF power is asserted to improve film stress. The barrier layers are preferably produced from alkoxysilanes or chlorinated alkylsilanes and N2O to reduce carbon content and increase the density of the layers.
The ""570 patent does not identify process conditions for making barrier layers having low dielectric constants or for making etch stop layers having high oxide contents. The ""570 patent also does not suggest use of the described layers as a barrier layer adjacent a low k dielectric layer or as an etch stop.
There remains a need for dielectric layers having low dielectric constants, good barrier properties, and high oxide content for use as barrier layers or etch stop layers in sub-micron devices.
The present invention provides a method and apparatus for depositing a silicon oxide layer having a low dielectric constant. The silicon oxide layer is produced by plasma assisted chemical vapor deposition of an organosilane, an organosiloxane, or combinations thereof, using RF or microwave power to generate reactive oxygen atoms. The properties of the silicon oxide layers are readily controlled by process variations, and different layers can be deposited in one deposition chamber as shown for an improved dual damascene process. In addition, the silicon oxide layers can be used as an adhesive layer between different layers, or as an intermetal dielectric layer. A preferred silicon oxide layer is produced by reaction of nitrous oxide, N2O, and a silicon compound containing Sixe2x80x94H bonds, such as methylsilane, CH3SiH3, dimethylsilane, (CH3)2SiH2, or 1,1,3,3-tetramethyl-disiloxane, (CH3)2xe2x80x94SiHxe2x80x94Oxe2x80x94SiHxe2x80x94(CH3)2.
The silicon oxide layers are cured at low pressure and high temperature to stabilize properties. The silicon oxide layers are most preferably produced using separate applications of RF power to the deposition chamber to increase porosity of the deposited layers. The use of low levels of RF power is preferred at chamber pressures less than about 10 Torr. Microwave power is preferably provided to oxidizing gases in a dissociation chamber to control formation of reactive oxidizers without increasing the power level in the deposition chamber.
In a preferred embodiment, a silicon oxide layer is deposited on a patterned metal layer by plasma assisted reaction of one or more organosilane and/or organosiloxane compounds that include Sixe2x80x94H bonds.
The silicon oxide of the present invention has further utility in an integrated process for manufacture of reliable dual damascene structures in one deposition chamber to reduced capacitive coupling between interconnect lines. in a preferred embodiment, a low k dielectric film having high carbon content, greater than about 20% by atomic weight, is deposited as a via level dielectric layer. A low k dielectric film having a low carbon content, less than about 10% by atomic weight, is then deposited on the high carbon layer to form a trench level dielectric layer. A dual damascene etch then forms the trenches in the trench level dielectric layer and stops at the via level dielectric layer. After etching the vias in the via level dielectric layer, the upper surface is then planarized to leave a planar surface on the trench level dielectric layer.
The invention further provides an intermetal dielectric material (IMD) comprising the silicon oxide which is deposited on a conventional etch stop such as silicon oxide or silicon nitride. The silicon oxide can also be deposited as a thin adhesive layer.